Modern data storage systems for use with a host central processing unit (“CPU”) usually include at least one disc drive for nonvolatile storage. Each disc drive typically includes one or more discs upon which are one or two data surfaces with addressable tracks and storage sectors. The disc drive unit includes a read/write head for accessing data to be stored or read from each disc storage surface. In drives that use more than one data surface, the collection of all tracks having the same track number on the surfaces defines what is conventionally called a “storage cylinder.”
A disc controller is coupled between the host(s) and the storage device to control the flow of data and to control positioning of the disc read/write heads for accessing desired sectors. Data that the host CPU wants to store on a disc is first stored in a buffer memory accessible by the controller. The controller then reads the buffer memory and writes the data to the disc at storage locations specified by the host CPU. Data that the host wants to retrieve from the disc is requested by the host CPU and retrieved from disc to the buffer memory. The data is then sent to the host by the disc controller via a host interface.
The host CPU specifies memory storage locations in terms of physical disc addresses, for example, by specifying disc cylinder, head and sector at which the desired data is to be found or stored. On the other hand, modern computer systems preferably use logical (or “virtual”) addressing, with which data is identified by a logical sector address. The necessary physical-logical address conversions take place under control of a local microprocessor associated with the disc controller unit. Generally, to be competitive in the commercial market place, the local microprocessor is a relatively inexpensive, low performance component.
When the host CPU sends a command to the disc controller, task registers within the controller are written to and initialized, for example with respect to sector, head, transfer count, and mode information. The last action associated with this process is the writing of the actual command, e.g., a read command, to the command register within the task registers. Certain bits within the host CPU-issued command inform the disc controller what type of address is being given, e.g., physical CHS or virtual LBA. However, these command bits do not inform the controller as to what action should be taken.
As noted, the first few writes by the host CPU simply load information into the other task registers. The final write is to the command register, at which time the local microprocessor recognizes that this register has been written to. Upon recognition, which can result from polling or from an interrupt mechanism, the local microprocessor fetches the contents of all of the registers. The number of task registers depends upon the standard to which the disc controller conforms. For example, an AT Attachment (or “ATA”) compatible controller may have six to ten task registers, whereas a Small Computer System Interface (“SCSI”) controller can have sixteen or more registers. These registers are used, for example, to specify the addresses at which the host CPU wishes to read or write.
Unfortunately, conventional protocols offer little or no control over how queued commands are to be performed. The SCSI protocol has a “head of queue” modifier available as a part of its command delivery sequence, for example, to expedite certain commands. Exclusive reliance on such modifiers wastes a valuable opportunity for efficient and versatile control over how queued commands are executed.